To design digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
Generally, a verification application is used to generate tests for a system-on-chip (SoC) verification. The verification application is often used to verify standard bus protocols. As designs incorporate more (and more complex) standard interfaces, the engineers tasked with verifying the behavior of those designs find themselves faced with a barrage of new challenges: they need to understand the detailed operation of the incorporated bus protocols and how those protocols interact with each other and the design. For new interfaces such as USB 3.0 or AMBA 4, or even a well-established interface, this may represent a significant effort. Large SoCs that incorporate multiple protocols exacerbate these issues.
Typically, the scope of recent protocol definitions extends from the lowest physical details, such as the analog behavior exhibited by a physical layer of an Open Systems Interconnection (OSI) model (PHY), up to the edge of (and sometimes into) the software domain. Traditional debug methodologies that utilize waveforms and simulation log files as their source of information are insufficient for understanding the complex hierarchy and inter-relationships of transfers, transactions, data packets and handshaking that are typical of modern protocol specifications.
FIG. 1 shows a traditional graphical user interface 100 having a waveform window 101 and a simulation log file window 102 to analyze design of the integrated circuits. Analysis of high-level protocol behavior in designs that incorporate complex, interleaved bus protocols is difficult using the waveform window 101 and simulation log file 102. Generally, a single waveform shown in window 101 represents bits on a very low (e.g., PHY) level of presentation. It is very difficult and time consuming for a user to understand which portion of the waveform in window 101 correspond to which protocol activity by looking on the log information in window 102. It requires a user to make a lot of notes and calculations about when an activity started and stopped and which activities are going on at the same time. Traditional protocol debug methods that use waveforms and simulation logs are time-consuming and error-prone.